The present disclosure relates to a semiconductor memory device and, more particularly, to a circuit technology for solving a problem which occurs when a ground voltage is applied to a memory cell during a program operation.
In recent years, with growing demand for electronic equipment, particularly mobile phones, mobile music players, digital cameras, and the like, demand for semiconductor devices, particularly flash memories has grown. As a result, vigorous technological development has been undertaken to achieve a larger capacity, a smaller size, a higher-speed program, and a higher-speed read operation.
As a technology for implementing a larger-capacity flash memory, there has been a multi-level technique for a memory cell. According to the multi-level technique, data of 2 bits or more is stored in a memory cell. To implement the multi-level technique, a flash memory using a MONOS memory cell (NROM) has been vigorously developed in recent years. The MONOS flash memory implements multi-level data storage by storing data at physically different two locations in a memory cell, and is used as a flash memory for, e.g., storing the code program of electronic equipment.
A program operation in the MONOS flash memory is performed by applying a positive high voltage of about 9 V to the gate of a memory cell, applying a positive high voltage of about 3 to 6 V to the drain thereof, and applying a ground voltage of 0 V to the source thereof. The program operation in the MONOS flash memory is performed through a CHE (Channel Hot Electron) operation, and a cell current during the program operation has a value as large as about 100 to 200 μA.
FIG. 8 is a view showing a current path during a program operation in a conventional MONOS flash memory. In FIG. 8, a memory cell MC has a gate connected to a word line WL0, a drain connected to a sub-bit line SBL1, and a source connected to a sub-bit line SBL0. The sub-bit lines SBL0 and SBL1 are connected respectively to main bit lines MBL0 and MBL1 via selection transistors S0 and S1. To the respective gates of the selection transistors S0 and S1, selection transistor control signals SL0 and SL1 are given. During the program operation to a memory cell MC, the selection transistor control signals SL0 and SL1 are each in a selected state, while the sub-bit lines SBL0 and SBL1 and the main bit lines MBL0 and MBL1 are each in a connected state.
The main bit lines MBL0 and MBL1 are connected respectively to first column transistors C0 and C1. To the respective gates of the first column transistors C0 and C1, first column transistor control signals CS0 and CS1 are given. During the program operation to the memory cell MC, the first column transistor selection signals CS0 and CS1 are each in the selected state. The first column transistors C0 and C1 are connected respectively to second column transistors B0 and B1. To each of the respective gates of the second column transistors B0 and B1, a second column transistor control signal BS0 is given. During the program operation to the memory cell MC, the second column transistor control signal BS0 is in a selected state.
The second column transistor B1 is connected to a drain voltage application transistor T1, while the second column transistor B0 is connected to a ground voltage application transistor T0. During the program operation, the drain voltage application transistor T1 applies a positive high voltage VPPD to the drain of the memory cell MC, while the ground voltage application transistor T0 applies a ground voltage of 0 V to the source of the memory cell MC.
That is, during the program operation, the positive high voltage VPPD is applied to the drain of the memory cell MC via the drain voltage application transistor T1, the second column transistor B1, the first column transistor C1, the main bit line MBL1, the selection transistor S1, and the sub-bit line SBL1. On the other hand, the ground voltage of 0 V is applied to the source of the memory cell MC via the ground voltage application transistor T0, the second column transistor B0, the first column transistor C0, the main bit line MBL0, the selection transistor S0, and the sub-bit line SBL0.